With increasing integration of semiconductor devices, channel lengths decrease continuously for MOSFETs. A series of effects that are negligible in a long channel model of the MOSFET become increasingly obvious, or even become dominant factors influencing performances of the devices. These effects are generally referred to as short channel effects, which may deteriorate electrical performances of the devices. For example, the short channel effects may cause problems such as decreased gate threshold voltage, increased power consumption, degraded signal-to-noise ratio, or the like.
Currently, in order to solve the problems of the short channel effects, a three-dimensional (3C) device structure of FinFET is proposed. The FinFET is a transistor having a fin-type channel structure, which uses several surfaces of a thin fin as channels, so as to avoid the short channel effects in the conventional transistors while increasing an operation current.
In the existing manufacture processes for the FinFET, in order to reduce a leakage current between the source region and the drain region, a Punch-Trough-Stop Layer (PTSL) may be formed at a lower portion of the fin. Generally, the PTSL is formed in the fin by ion implantation after the fin and an isolation layer is formed. However, there is a problem as follows. Specifically, due to non-uniformity of doping concentration in the PTSL at edges of the fin, the leakage current between the source region and the drain region increases and the short channel effects become more significant with continuous decreasing of the gate length (especially when less than 20 nm).